The Symmetrical Cascode OTA
Verification
Christian Enz
Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland
Initilization¶
Introduction¶
Schematic of the symmetrical OTA.
This notebook presents the design of the symmetrical cascode OTA which schematic is shown in the above figure. Note that all nMOS transistors have an odd number and all the pMOS transistors an even number which explains the numbering process. We will design the circuit with M1a-M1b in a separate well.
OTA Characteristics¶
Sizing summary¶
Process parameters¶
Specifications¶
Bias information¶
Transistors information¶
Open-loop gain¶
We can plot the magnitude and phase of the open-loop gain.
Input-referred noise¶
We now can estimate the input-referred noise PSD.
We see that the OTA thermal noise excess factor is only slightly larger than that of the differential pair. This is due to the rather large $G_{m1}/G_{m2}$ and $G_{m1}/G_{m3}$ ratios.
We can now compute the input-referred flicker noise and the corner frequency.
We see that the current mirrors contribute about the same than the differential pair.
We can plot the input-referred noise
Input-referred offset¶
The variance of the input-referred offset for $A_1=A_2=A_3=1$ is given by \begin{equation} \sigma_{V_{os}}^2 = \sigma_{V_{T1}}^2 \cdot (1 + \xi_{V_T}) + \left(\frac{I_b}{G_{m1}}\right)^2 \cdot \sigma_{\beta 1}^2 \cdot (1 + \xi_{\beta}) \end{equation} where \begin{align} \xi_{V_T} &= 2\left(\frac{G_{m2}}{A_1\,G_{m1}}\right)^2 \cdot \left(\frac{A_{VTp}}{A_{VTn}}\right)^2 \cdot \frac{W_1 L_1}{W_2 L_2} + \left(\frac{G_{m3}}{G_{m1}}\right)^2 \cdot \frac{W_1 L_1}{W_3 L_3},\\ \xi_{\beta} &= 2\left(\frac{A_{\beta p}}{A_{\beta n}}\right)^2 \cdot \frac{W_1 L_1}{W_2 L_2} + \frac{1}{A_1^2} \cdot \frac{W_1 L_1}{W_3 L_3}. \end{align} with \begin{align} \sigma_{V_{T1}}^2 &= \frac{A_{VTn}^2}{W_1 L_1},\\ \sigma_{V_{T2}}^2 &= \frac{A_{VTp}^2}{W_2 L_2},\\ \sigma_{V_{T3}}^2 &= \frac{A_{VTn}^2}{W_3 L_3}, \end{align} and \begin{align} \sigma_{\beta 1}^2 &= \frac{A_{\beta n}^2}{W_1 L_1},\\ \sigma_{\beta 2}^2 &= \frac{A_{\beta p}^2}{W_2 L_2},\\ \sigma_{\beta 3}^2 &= \frac{A_{\beta n}^2}{W_3 L_3}. \end{align}
We see that the $\beta$-mismatch is negligible and that the input-referred offset voltage is dominated by the contribution of the $V_T$-mismatch from the differential pair.
Current and power consumption¶
The total current consumption, ignoring the current drawn by \M{5a}, is $I_{tot} = (2+A_1+A_3) \cdot I_b$. Assuming the input differential pait M1a-M1b is biased in weak inversion, the bias current is directly related to the gain-bandwidth product $GBW$ according to \begin{equation} I_b \cong n U_T \cdot \frac{C_L}{A_3} \cdot GBW. \end{equation} The total current consumption can then be written as \begin{equation} I_{tot} \cong \frac{2+A_1+A_3}{A_3} \cdot n U_T \cdot C_L \cdot GBW. \end{equation} The bias current and the total current are proportional to the gain-bandwidth product $GBW$ and the load capacitance $C_L$. In the case $A_1=A_2=A_3=1$, $I_{tot} \cong 4 \cdot n U_T \cdot C_L \cdot GBW$.
Simulation results from Smash¶
The theoretical results can be compared with results obtained from simulations performed with Smash. The cells below will run the simulations with Smash. In order to run the simulations you need to have Smash installed in the default directory.
Saving parameter file¶
We first write the parameter file for this specific design for running the Smash simulations.
Operating point¶
To start we need to check the quiescent voltages and currents and the operating points of all transistors by running a .OP simulation.
We can check the operating point information looking the .op file.
Looking at the .op file, we see the output voltage is too low and is pushing M7 and M3b out of saturation. This due to the current mismatch in M2c and M2d and between M3a and M3b due to different drain voltages and finite output conductances leading to a different current flowing in M2d and M4 compared to that flowing in M3b and M7. Even if the current difference is very small, it results in a large voltage debiasing at the output because of the high output resistance provided by the cascode stages.
Therefore simulating the open-loop gain for high gain amplifiers is not easy to perform without closing the loop. There are basically two approaches to simulate the open-loop gain for high-gain amplifiers: 1) Imposing a DC offset voltage to the amplifier in open-loop configuration that brings the output voltage back to normal (for example equal to the input common-mode voltage) or 2) Simulating the closed-loop gain (for example in voltage follower mode with a feedback gain of 1) and extracting the open-loop gain from the closed loop gain according to \begin{equation*} A_{open\textsf{-}loop}(\omega)= \frac{A_{closed\textsf{-}loop}(\omega)}{1 - A_{closed\textsf{-}loop}(\omega)}, \end{equation*} where $A_{closed\textsf{-}loop}(\omega)$ is the simulated closed-loop transfer function and $A_{open\textsf{-}loop}(\omega)$, the computed open-loop transfer function. The above relation assumes that the open-loop DC gain is large enough for the input-referred offset voltage to be ignored.
The input-referred offset voltage can be extracted from the closed-loop voltage follower circuit as \begin{equation*} V_{os} = V_{in} - \left(1+\frac{1}{A}\right) \cdot V_{out} \cong V_{in} - V_{out} \quad \textsf{for $A \gg 1$}, \end{equation*} where $A \triangleq A_{open\textsf{-}loop}(0)$ is the open-loop DC gain which can be assumed to be much larger than 1. This means that, provided the DC open-loop gain is sufficiently large, the offset voltage can be measured at the amplifier differential input after imposing the proper input common-mode voltage $V_{ic}$.
We can now simulate the OTA in closed-loop as a voltage follower.
Let's have a look at the operating point information.
We see that now all the transistors are biased in saturation and that the quiescent output voltage $V_{outq}$ is very close to the input common-mode voltage.
The difference is actually the offset voltage $V_{os}$.
We can apply this offset voltage to the open-loop circuit and check the operating point.
We see that now all the transistors are biased in saturation and that the quiescent output voltage $V_{outq}$ is very close to the input common-mode voltage.
Large-signal differential transfer characteristic¶
In order to simulate the small-signal diferential open-loop gain we first need to check the differential transfer characteristic in order to find the eventual offset voltage that needs to be added to make sure the output voltage is set at the common-mode voltage.
The extracted output voltage swing does actually not correspond to the swing of the linear part. We need to zoom into the linear gain region.
Open-loop gain¶
From closed-loop gain simulation¶
In Smash it is unfortunately not possible to export the complex value of the closed-loop gain in batch mode simulation. We can verify this approach using the Smash interface.
From open-loop simulation¶
Having extracted the offset voltage to make sure that the output voltage is close to the input common-mode voltage, we can now simulate the open-loop gain.
We see a very good match between the small-signal simulations and the theoretical results. We see some discrepancy above the $GBW$, because of additional poles due to parasitic capacitances that have not been accounted for and introduce additional phase shift.
Input-referred noise¶
We can compare the theoretical input-referred noise to that obtained from simulations.
Again, there is a good match between the noise simulations and the theoretical results except at frequencies above the unity-gain frequency (1 MHz). As explained above, this is simply due to the fact that the noise coming from all the transistors except that coming from the differential pair M1a-M1b are referred to the input by dividing by the square of the dc gain instead of the square magnitude of the frequency-dependent gain.
As expected the input-referred noise is dominated by the contribution of the differential pair M1a-M1b. The pMOS current mirrors M2a-M2b and M2c-M2d are contributing slightly less, whereas the contribtuion of the nMOS current mirror M3a-M3b is much less. Finally the contributions of the cascode transistors M4 and M7 are negligible.
Input-referred offset voltage¶
The standard deviation of the random input-referred offset voltage can be simulated in Smash using Monte-Carlo (MC) simulation with 1000 runs. Note that the matching parameters have to be converted to dispersion parameters according to \begin{align*} SIGMAV &= \frac{A_{VT}}{\sqrt{2}},\\ SIGMAI &= \frac{A_{\beta}}{\sqrt{2}}. \end{align*} for both NMOS and pMOS.
The offset voltage is first extracted from the open-loop circuit as shown in Fig. \ref{fig:open_loop_offsetvoltage}. The results of the MC simulation is $\sigma{Vos} = 3.73\,mV$ which is consistent with the dispersion simulation $\sigma{Vos} = 3.77\,mV$ provided by Smash and close to the theoretical estimations $\sigma{Vos} = 3.68\,mV$.
MC simulation of the open-loop transfer characteristic for extracting the offset voltage.
For high gain amplifiers, it is also possible to measure the offset by putting the OPAMP in a closed loop as shown in Fig. \ref{fig:closed_loop_offsetvoltage}. The results of the MC simulation is $\sigma{Vos} = 3.75\,mV$ which is consistent with the dispersion simulation $\sigma{Vos} = 3.77\,mV$ provided by Smash and close to the theoretical estimations $\sigma{Vos} = 3.68\,mV$.
MC simulation using a closed-loop configuration for extracting the offset voltage.
Contribution of the various transistors to the input-referred offset is shown in Fig. \ref{fig:closed_loop_offset_contributions}. It confirms that the differential is the dominant contributor to the offset voltage.
MC closed-loop simulation of the contributions of the differential pair and the current mirror to the input-referred offset.
Power consumption¶
The total power consumption is given by
The power consumption of the symmetrical OTA is about 1.5 times larger than that of the simple OTA.
Simulation results from ngspice¶
The theoretical results can also be compared with results obtained from simulations performed with ngspice. The cells below will run the simulations with ngspice. In order to run the simulations you need to have ngspice installed. Please refer to the moodel site for full instructions.
Saving parameter file¶
We first write the parameter file for this specific design for running the ngspice simulations.
Operating point¶
The voltages at the various circuit nodes are given below.
Looking at the .op file, we see the output voltage is too low and is pushing M7 and M3b out of saturation. This due to the current mismatch in M2c and M2d and between M3a and M3b due to different drain voltages and finite output conductances leading to a different current flowing in M2d and M4 compared to that flowing in M3b and M7. Even if the current difference is very small, it results in a large voltage debiasing at the output because of the high output resistance provided by the cascode stages.
Therefore simulating the open-loop gain for high gain amplifiers is not easy to perform without closing the loop. There are basically two approaches to simulate the open-loop gain for high-gain amplifiers: 1) Imposing a DC offset voltage to the amplifier in open-loop configuration that brings the output voltage back to normal (for example equal to the input common-mode voltage) or 2) Simulating the closed-loop gain (for example in voltage follower mode with a feedback gain of 1) and extracting the open-loop gain from the closed loop gain according to \begin{equation*} A_{open\textsf{-}loop}(\omega)= \frac{A_{closed\textsf{-}loop}(\omega)}{1 - A_{closed\textsf{-}loop}(\omega)}, \end{equation*} where $A_{closed\textsf{-}loop}(\omega)$ is the simulated closed-loop transfer function and $A_{open\textsf{-}loop}(\omega)$, the computed open-loop transfer function. The above relation assumes that the open-loop DC gain is large enough for the input-referred offset voltage to be ignored.
The input-referred offset voltage can be extracted from the closed-loop voltage follower circuit as \begin{equation*} V_{os} = V_{in} - \left(1+\frac{1}{A}\right) \cdot V_{out} \cong V_{in} - V_{out} \quad \textsf{for $A \gg 1$}, \end{equation*} where $A \triangleq A_{open\textsf{-}loop}(0)$ is the open-loop DC gain which can be assumed to be much larger than 1. This means that, provided the DC open-loop gain is sufficiently large, the offset voltage can be measured at the amplifier differential input after imposing the proper input common-mode voltage $V_{ic}$.
We can now simulate the OTA in closed-loop as a voltage follower.
We see that now the ouput voltage is very close to the input voltage that has been set to $V_{ic}$. We can then extract the corresponding offset voltage $V_{os} \cong V_{in} - V_{out}$
We can now apply this offset voltage to the open-loop operating point point simulation.
The operating point information for all transistors can be extracted from the .op file.
We can check the bias voltages and operating region of each transistor below.
The output voltage in open-loop is now close to the common-mode input voltage $V_{ic}$. We can now proceed with the simulation of the open-loop large-signal transfer characteristic.
Large-signal differential transfer characteristic¶
We now simulate the DC differential transfer characteristic. We can then check the systematic offset voltage that was extracted above.
We can now zoom into the high gain region and extract a more accurate value of the offset voltage.
Open-loop gain¶
Closed-loop circuit¶
As explained above we can extract the open-loop gain from the simulated closed-loop gain with the amplifier operating as a voltage follower. The open-loop gain is then given by \begin{equation*} A_{open\textsf{-}loop}(\omega)= \frac{A_{closed\textsf{-}loop}(\omega)}{1 - A_{closed\textsf{-}loop}(\omega)}, \end{equation*} where $A_{closed\textsf{-}loop}(\omega)$ is the simulated closed-loop transfer function and $A_{open\textsf{-}loop}(\omega)$, the computed open-loop transfer function. The above relation assumes that the open-loop DC gain is large enough for the input-referred offset voltage to be ignored.
Note that we need to have a sufficient number of digits for the simulated closed-loop gain because the later is very close to 1.
Open-loop circuit¶
After having checked the operating point information, extracted the offset voltage and making sure that the OTA output is not saturated, we can now proceed with the open-loop gain simulation.
We see a very good match between the simulation and the theoretical prediction for the $GBW$. However, the simulated dc gain is higher than the predicted one, which is due to the poor output conductance model. But this is OK since it is larger than the specs.
Input-referred noise¶
We can compare the theoretical input-referred noise to that obtained from simulations.
We observe a very good match between the predicted and simulated input-referred noise which is completely dominated by the flicker noise contribution.
Conclusion¶
This notebook presented the detailed analysis and design of the symmetrical OTA. The analysis allowed to derive the design equations to achieve the target specifications. The latter have been checked by simulations with the Smash simulator. The simulations match the expected results derived from the analysis.